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SH67K91
20K 4-bit Micro-controller with LCD Driver, 4/8 channels Chord
Feature
- 32 Seg X 6 Com (1/6 duty, 1/3 or 1/4 Bias) SH6610C-Based Single-Chip 4-bit Micro-controller - 32 Seg X 8 Com (1/8 duty, 1/3 or 1/4 Bias) ROM: 20K X 16 bits 12 Segments Used as Scan Output RAM: 1437 X 4 bits 4/8 Channels Chords - 48 bytes System Control Register - 1325 bytes Data Memory 9 bits DAC - 64 bytes LCD RAM Oscillator (Code Option) Operation Voltage: 2.4V - 5.5V OSC - Crystal Oscillator 32.768kHz 16 CMOS Bi-directional I/O pads (8 shared with - RC Oscillator: 262kHz Segment) OSCX 4-Level Stacks (include interrupts) - Ceramic Resonator 455kHz - 4MHz One 8-bit Auto Re-load Timer/Counter - RC Oscillator 4MHz 8-bit Base Timer Instruction Cycle Time Powerful Interrupt Sources - 122.07s for 32.768 kHz Crystal - External Interrupt (falling edge) - 15.27s for 262 kHz RC - Timer0 Interrupt - 1s - Base Timer Interrupt .com for 4 MHz RC - External Interrupts: PORTB and PORTC Two Low Power Operation Mode: HALT and STOP LCD Driver Warm-up Timer for Power-On Reset (POR) - 32 Seg X 4 Com (1/4 duty, 1/3 or 1/4 Bias) Available In CHIP FORM - 32 Seg X 5 Com (1/5 duty, 1/3 or 1/4 Bias)
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General Description
SH67K91 is a single-chip 4-bit micro-controller. This device integrates a SH6610C CPU core, RAM, ROM, Timer, LCD driver, I/O port, 4/8 channels chord and DAC. This chip contains a built-in dual-oscillator to enhance the total chip performance. This device is suitable for simple CID cord phone.
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V1.0
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SH67K91
Pad Configuration
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
41
SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 PORTB0 PORTB1 PORTB2 PORTB3 PORTA0 PORTA1 PORTA2
20 19 18 17 16 15 14 13 12 11 10 9 8 7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG5
42 43 44 45 46 47 48 49 50 51
SEG4 SEG3 SEG2 SEG1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8
SH67K91
52 53 54
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PORTA3 B0 GND RING TIP AVDD B1 DACOUT TONE
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55
VDD OSCO OSCI OSCXO OSCXI RESET TEST
6 5 4 3
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56 57 58 59 60 61
2 1
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SH67K91
Block Diagram
ROM (20K X 16) RAM (1.4K X 4) 8-BIT TIMER0 8-BIT Base Timer OSC OSCX
OSCI OSCO OSCXI OSCXO
PORTB
PORTB[0:3]
PORTA & EXTERNAL INT CPU COMMON DRIVER
RESET TEST
PORTA.0/INT0 PORTA.1 PORTA.2 PORTA.3 COM[8:1]
SEG[29:32]/PORTC
LCD RAM
SEGMENT DRIVER
SEG[25:28]/PORTD SEG[13:24]/SCAN OUTPUT SEG[1:12]
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iDAC
AVDD VDD GND
FSK/DTMF DECODER
TIP RING
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DACOUT TONE
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SH67K91
Pad Description (Total 61 Pads)
Pad No. 55 3 6 61 60 58 59 56 57 7 - 10 11 - 14 15 - 18 19 - 22 Designation VDD AVDD GND TEST RESET OSCXO OSCXI OSCO OSCI PORTA3 - PORTA0 PORTB3 - PORTB0 SEG32 - SEG29 /PORTC3 - PORTC0 SEG28 - SEG25 /PORTD3 - PORTD0 SEG24 - SEG13 SEG12 - SEG1 COM8 - COM1 TIP RING DACOUT TONE I/O P P P I I O I O I I/O I/O O/ I/O O/ I/O O O O I I O O Power supply Power supply Ground pad Test pad (Internal pull-low). No connection for user Reset input (No internal pull-high) High Speed Oscillator output pad High Speed Oscillator input pad Low Speed Oscillator output pad Low Speed Oscillator input pad Bit programmable I/O, PA0 shared with INT0 Bit programmable I/O, Vector interrupt ( INT1 ) Segment signal output for LCD display Share with PORTC Segment signal output for LCD display Share with PORTD Segment signal output for LCD display Share with scan output Description
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23 - 34 35 - 46 54 - 47 4 5 2 1
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Segment signal output for LCD display
Common signal output for LCD display Connected with TIP side & Ring side for twisted pair DAC output Tone output
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SH67K91
Functional Description
1. CPU 1.4. Table Branch Register (TBR) The CPU contains the following functional blocks: Program Counter (PC), Arithmetic Logic Unit (ALU), Carry Table Data can be stored in program memory and can be Flag (CY), Accumulator, Table Branch Register, Data referenced by using Table Branch (TJMP) and Return Pointer (INX, DPH, DPM, and DPL) and Stacks. Constant (RTNW) instructions. The TBR and AC are 1.1. PC placed by an offset address in program ROM. TJMP instruction branch into address ((PC11 - PC8) X (28) + The PC is used for ROM addressing consisting of 12-bit: (TBR, AC)). The address is determined by RTNW to return Page Register (PC11), and Ripple Carry Counter (PC10, look-up value into (TBR, AC). ROM code bit7-bit4 is PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). placed into TBR and bit3-bit0 into AC. The program counter is loaded with data corresponding to 1.5. Data Pointer each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K. The Data Pointer can indirectly address data memory. The program counter can only include 4K program ROM Pointer address is located in register DPH (3-bit), DPM address. (Refer to the ROM description). (3-bit) and DPL (4-bit). The addressing range can have 3FFH locations. Pseudo index address (INX) is used to 1.2. ALU and CY read or write Data memory, then RAM address bit9 - bit0 The ALU performs arithmetic and logic operations. The which comes from DPH, DPM and DPL. ALU provides the following functions: 1.6. Stack Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) The stack is a group of registers used to save the contents Decimal adjustments for addition/subtraction (DAA, DAS) of CY & PC (11-0) sequentially with each subroutine call or Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) interrupt. The MSB is saved for CY and it is organized into Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC) 13 bits X 4 levels. The stack is operated on a first-in, Logic Shift (SHR) last-out basis and returned sequentially to the PC with the The Carry Flag (CY) holds the ALU overflow that the return instructions (RTNI/RTNW). arithmetic operation generates. During an interrupt service Note: or a CALL instruction, the carry flag is pushed into the The stack nesting includes both subroutine calls and stack and recovered from the stack by the RTNI interrupts requests. The maximum levels allowed for instruction. It is unaffected by the RTNW instruction. .com calls and interrupts are 4 levels. If the number subroutine 1.3. Accumulator (AC) of calls and interrupt requests exceeds 4, then the bottom The accumulator is a 4-bit register holding the results of of the stack will be shifted out, that program execution may the arithmetic logic unit. In conjunction with the ALU, data enter an abnormal state. is transferred between the accumulator and system register, or data memory can be executed.
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2. RAM Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data after the CPU enters STOP or HALT. 2.1. RAM Addressing Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory allocation map: System register and I/O: $000 - $02F Data memory: $030 - $2FF, $340 - $3FF, $430 - $5CF (total 1325 X 4 bits) Reserved: $5D0- $5FF LCD RAM space: $300 - $33F RAM Mapping $000 - $02F $400 - $42F $030 - $2FF $300 - $33F $340 - $3FF $430 - $5CF $5D0-$5FF System Register Data Memory LCD Display memory Data Memory Reserved
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Note: $400 - $42F and $000 - $02F refer to the same System Register. RAM bank table: (RAMBNK: System Register RAMBNK0) RAMBNK0 =0 RAMBNK0 =1 Bank 0 B = 000 Bank 8 B = 000 Bank 1 B = 001 Bank 9 B = 001 Bank 2 B = 010 Bank 3 B = 011
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Bank 4 B = 100 Bank 5 B = 101 Bank 6 B = 110 Bank 7 B = 111
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$000 - $07F $080 - $0FF $100 - $17F $180 - $1FF $200 - $27F $280 - $2FF $300 - $37F $380 - $3FF Bank 10 B = 010 Bank 11 B = 011
$430 - $47F $480 - $4FF $500 - $57F $580 - $5FF
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SH67K91
2.2 Configuration of System Register The Configuration of System Register Address $00 $01 $02 $03 $04 Bit 3 IEX IRQX TM0.3 BTM.3 T0L.3 TC0L.3 TL0H.3 TC0H.3 BTC.7 BTC.3 PA.3 PB.3 PC.3 PD.3 PPULL Bit 2 IET0 IRQT0 TM0.2 BTM.2 T0L.2 TC0L.2 TL0H.2 TC0H.2 BTC.6 BTC.2 PA.2 PB.2 PC.2 PD.2 HLM Bit 1 IEBT IRQBT TM0.1 BTM.1 T0L.1 TC0L.1 TL0H.1 TC0H.1 BTC.5 BTC.1 PA.1 PB.1 PC.1 PD.1 OXM Bit 0 IEP IRQP TM0.0 BTM.0 T0L.0 TC0L.0 TL0H.0 TC0H.0 BTC.4 BTC.0 PA.0 PB.0 PC.0 PD.0 OXON R/W R/W R/W R/W R/W W R W R R R R/W R/W R/W R/W R/W Interrupt enable flags Interrupt request flags Timer0 mode register Base timer mode register Timer0 load low nibble Timer0 counter low nibble Timer0 load high nibble Timer0 counter high nibble High nibble of Base Timer counter Low nibble of Base Timer counter PORTA data register PORTB data register PORTC data register PORTD data register Bit0: Turn on OSCX oscillator $0C Remarks
$05 $06 $07 $08 $09 $0A
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$0B
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Bit2: Heavy load mode Bit3: Port pull-high control for Port excluding PA0 Bit3: RAM Bank control bit Bit2 - 0: LCD contrast adjustment register Table branch register Index register (INX) Data pointer for INX low nibble Data pointer for INX middle nibble Data pointer for INX high nibble Bit1 - 0: segment/PORTC - D sharing control bits Bit2: Segment/scan output control bit for segment13 - 24 Bit3: LCD on/off control bit Bit0: Lcd frame frequency selection bit Bit1: Lcd Bias selection bit Bit3 - 2: duty selection bit Set PORTA to be input/output port Set PORTB to be input/output port Set PORTC to be input/output port Bit3: PA0 interrupt request flag Bit2: FSKIN interrupt request flag Bit1 - 0: Bonding Option
$0D $0E $0F $10 $11 $12 $13
RAMBNK TBR.3 INX.3 DPL3 LCDON
LCM2 TBR.2 INX.2 DPL2 DPM.2 DPH.2 O/S2
LCM1 TBR.1 INX1 DPL1 DPM.1 DPH.1 O/S1
LCM0 TBR.0 INX.0 DPL0 DPM.0 DPH.0 O/S0 LCD _FREQ PACR.0 PBCR.0 PCCR.0 B0
R/W R/W R/W R/W R/W R/W R/W
$14 $15 $16 $17 $18
COM_MD1 COM_MD0 PACR.3 PBCR.3 PCCR.3 IRQ_PA0 PACR.2 PBCR.2 PCCR.2 IRQ _FSKIN
BIAS PACR.1 PBCR.1 PCCR.1 B1
R/W R/W R/W R/W R/W R/W R R
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SH67K91
The Configuration of System Register (continued) Address $19 $1A $1B $1C Bit 3 TM0.4 DAC _S3 CH_M TONE7 DG7 DA7 TONE3 DG3 DA3 VOL 3 Bit 2 PDCR DAC _S2 CH_S2 TONE10 DG10 TONE6 DG6 DA6 TONE2 DG2 DA2 VOL 6 VOL 2 Bit 1 DAC _S1 CH_S1 TONE 9 DG9 TONE5 DG5 DA5 TONE1 DG1 DA1 VOL 5 VOL 1 Bit 0 DAC _S0 CH_S0 TONE 8 DG8 DA8 TONE4 DG4 DA4 TONE0 DG0 DA0 VOL 4 VOL 0 R/W R/W R/W R/W R/W Remarks Bit3: the clock source selection bit of timer 0 Bit2: Set PORTD to be input/output port DAC function control bit Bit2 - 0: Channel number of Melody selection bits Bit3: chord mode selection bit Prescaler register for Tone generator High nibble of DAC data register Counter register for Tone generator Middle nibble of DAC data register Counter register for Tone generator Low nibble of DAC data register Bit 3 - 0: Rom Bank Register Volume register of Melody
$1D
R/W
$1E $1F $20 $21
R/W
ROMBNK3 ROMBNK2 ROMBNK1 ROMBNK0 R/W R/W R/W
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$22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D RDT.3 RDT.7 RDT.11 RDT.15 SEG24 SEG20 SEG16 RDT.2 RDT.6 RDT.10 RDT.14 SEG23 SEG19 SEG15 AMP_ON RDT.1 RDT.5 RDT.9 RDT.13 SEG22 SEG18 SEG14 -
Reserved
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RDT.0 RDT.4 RDT.8 RDT.12 SEG21 SEG17 SEG13 R/W R/W R/W W R
R/W
Bit1: Amplifier power switch
Read Data Table address Read Data register
Scanning output Port Control register
Reserved Reserved Reserved Bit3: Pull-high/low resistor control bit of PA0 0: Pull-high/low resistor disable 1: Pull-high/low resistor enable Bit2: Pull-low or pull-high resistor selection control bit of PA0 0: Pull-high resistor enable, Pull-low resistor disable 1: Pull-high resistor disable, Pull-low resistor enable Bit1: Interrupt mode of PA0 (one source of INT0) 0: falling edge interrupt of PA0 1: Rising edge interrupt of PA0 Bit0: DAC output pad selection 0: DAC output from TONE pad 1: DAC output from DACOUT pad Reserved
$2E
PA0_PEN
PL/PH
INT0_PA0
DACOUT _S
R/W
$2F
-
-
-
-
-
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SH67K91
3. ROM The ROM can address 20480 words X 16 bits of program area from $0000 to $4FFF. 3.1 Vector Address Area ($000 to $004) The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address. Address $000 $001 $002 $003 $004 Instruction JMP* JMP* JMP* JMP* JMP* Remarks Jump to RESET service routine Jump to INT0 or FSKIN service routine Jump to Timer0 service routine Jump to Base timer service routine Jump to INT1 service routine
*JMP instruction can be replaced by any instruction. 3.2 ROM Data Read Table (RDT) System Register Address $24 Bit 3 RDT.3 RDT.7 RDT.11 RDT.15 Bit 2 RDT.2 RDT.6 RDT.10 RDT.14 Bit 1 RDT.1 RDT.5 RDT.9 RDT.13 Bit 0 RDT.0 RDT.4 RDT.8 R/W R/W R/W R/W Remarks ROM Data table address/data register ROM Data table address/data register ROM Data table address/data register
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$25 $26 $27
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.com ROM Data table address/data register RDT.12 R/W
The RDT register consists of a 16-bit write-only PC address load register (RDT.15 - RDT.0) and a 16-bit read-only ROM table data read-out register (RDT.15 - RDT.0). To read out the ROM table data, users should write the ROM table address to RDT register first (high nibble first then low nibble). Then after one instruction, the right data will be put into RDT register automatically (write lowest nibble of address into register will start the data read-out action).
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SH67K91
3.3 Bank Switch Mapping Program Counter (PC11 - PC0) can only address 4K ROM Space. The bank switch technique is used to extend the CPU address space. The lower 2K of the CPU address space maps to the lower 2K of the ROM space (BANK0). The upper 2K of the CPU address space maps to one of the nineteen banks (BNK.3 - 0 = $00 - $08) of the upper 18K of the ROM. The bank switch mapping is as follows: CPU Address $000 - $7FF ROM Space BNK = $00 BNK = $01 BNK = $02 BNK = $03 BNK = $04 BNK = $05 BNK = $06 BNK = $07
0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF 0000 - 07FF (BANK 0) (BANK 0) (BANK 0) (BANK 0) (BANK 0) (BANK 0) (BANK 0) (BANK 0) 0800 - 0FFF 1000 - 17FF 1800 - 1FFF 2000 - 27FF 2800 - 2FFF 3000 - 37FF 3800 - 3FFF 4000 - 47FF $800 - $FFF (BANK 1) (BANK 2) (BANK 3) (BANK 4) (BANK 5) (BANK 6) (BANK 7) (BANK 8) CPU Address $000 - $7FF ROM Space BNK = $08
0000 - 07FF (BANK 0) 4800 - 4FFF $800 - $FFF (BANK 9)
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SH67K91
4. Initial State 4.1. System Register State Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B Bit3 IEX IRQX TM0.3 BTM.3 T0L.3 TC0L.3 TL0H.3 TC0H.3 BTC.7 BTC.3 PA.3 PB.3 PC.3 PD.3 PPULL RAMBNK TBR.3 INX.3 DPL3 LCDON COM_MD1 PACR.3 PBCR.3 PCCR.3 IRQ_PA0 TM0.4 DAC_S3 CH_M TONE7 DG7 DA7 Bit2 IET0 IRQT0 TM0.2 BTM.2 T0L.2 TC0L.2 TL0H.2 TC0H.2 BTC.6 BTC.2 PA.2 PB.2 PC.2 PD.2 HLM LCM2 TBR.2 INX.2 DPL2 DPM.2 DPH.2 O/S2 COM_MD0 PACR.2 PBCR.2 PCCR.2 IRQ_FSKIN PDCR DAC_S2 CH_S2 TONE10 DG10 TONE6 DG6 DA6 Bit1 IEBT IRQBT TM0.1 BTM.1 T0L.1 TC0L.1 TL0H.1 TC0H.1 BTC.5 BTC.1 PA.1 PB.1 PC.1 PD.1 OXM TBR.1 INX1 DPL1 DPM.1 DPH.1 O/S1 BIAS PACR.1 PBCR.1 PCCR.1 B1 DAC_S1 CH_S1 TONE 9 DG9 TONE5 DG5 DA5 Bit0 IEP IRQP TM0.0 BTM.0 T0L.0 TC0L.0 TL0H.0 TC0H.0 BTC.4 BTC.0 PA.0 PB.0 PC.0 PD.0 OXON TBR.0 INX.0 DPL0 DPM.0 DPH.0 O/S0 LCD_FREQ PACR.0 PBCR.0 PCCR.0 B0 DAC_S0 CH_S0 TONE 8 DG8 DA8 TONE4 DG4 DA4 Power-on Reset/Pin Reset 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx 0011 0000 0000 0000 0000 0001 0000 0000 0000 0000
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$0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C
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LCM1 LCM0 .com
$1D
0000
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SH67K91
System Register State (Continued) Address $1E $1F $20 $21 $23 $24 $25 $26 $27 $28 $29 $2A $2E Bit3 TONE3 DG3 DA3 ROMBNK3 VOL 3 RDT.3 RDT.7 RDT.11 RDT.15 SEG24 SEG20 SEG16 PA0_PEN Bit2 TONE2 DG2 DA2 ROMBNK2 VOL 6 VOL 2 RDT.2 RDT.6 RDT.10 RDT.14 SEG23 SEG19 SEG15 PL/PH Bit1 TONE1 DG1 DA1 ROMBNK1 VOL 5 VOL 1 AMP_ON RDT.1 RDT.5 RDT.9 RDT.13 SEG22 SEG18 SEG14 INT0_PA0 Bit0 TONE0 DG0 DA0 ROMBNK0 VOL 4 VOL 0 RDT.0 RDT.4 RDT.8 RDT.12 SEG21 SEG17 SEG13 DACOUT_S Power-on Reset/Pin Reset 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
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SH67K91
4.2. Others Initial States Others Program Counter (PC) CY Accumulator (AC) Data Memory 5. System Clock and Oscillator The oscillator generates the basic clock pulses that provide the system clock to supply CPU and on-chip peripherals. System clock = fOSC/4 5.1 Instruction Cycle Time: (1) 4/32.768kHz (122.12s) for 32.768kHz oscillator. (2) 4/262kHz( 15.27s) for 262kHz oscillator. (3) 4/455kHz ( 8.79s) for 455kHz oscillator. (4) 4/4MHz (= 1s) for 4MHz oscillator. 5.2 Circuit Configuration SH67K91 has two on-chip oscillation circuits OSC and OSCX. OSC is a low frequency oscillator (32.768kHz crystal) or RC (Typ. 262kHz) determined by the code option. OSCX also has two types: ceramic (455kHz - 4MHz) or RC (4MHz) determined by code option. It is designed for high frequency operation. It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low operation clock. At the start of reset initialization, the OSC starts oscillation and OSCX is turned off. Immediatly after reset initialization, the OSC clock is automatically selected as the system clock input source. Oscillator Block Diagram
OSCI OSCO
After any Reset $000 Undefined Undefined Undefined
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Low Frequency Oscillator System clock Source Selector
OSCXI OSCXO
Base Timer
System clock
& Switching control
Generator
CPU Clock
High Frequency Oscillator
Timing of System Clock Switching
OSCX turn off OSCX turn on
OSCX
OSCO
SYS CLOCK
High frequency operation Low frequency operation High frequency operation
Switch from OSCX to OSC
Switch from OSCX to OSC
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5.3. OSC Oscillation The OSC generates the basic clock pulses that provide the CPU and peripherals (Timer0, BaseTimer, LCD) with an operating clock. (1) OSC Crystal oscillator type
32.768kHz C1 OSCI Crystal OSCO C2 15p (for reference only) 15p (for reference only)
(2) OSC RC oscillator type
ROSC OSCI 120k (for reference only) VDD
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5.4. OSCX Oscillator OSCX has two clock oscillators. The code options select the Ceramic or RC as the CPU's clock. If the OSCX is not used, it must be masked into Ceramic resonator and the OSCXI must be connected to GND. (1) OSCX Ceramic oscillator type
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C1 OSCXI Ceramic OSCXO 455kHz - 4MHz C2
30p (for reference only)
30p (for reference only)
(2) OSCX RC oscillator type
ROSC OSCXI 130k (for reference only) VDD
5.5 Control of Oscillator The oscillator control register configuration is shown as follows: Address $0C Bit3 PPULL Bit2 HLM Bit1 OXM Bit0 OXON R/W R/W Remarks Bit0: Turn on OSCX oscillator Bit1: CPU clocks select (1:OSCX /0:OSC)
OXON: OSCX oscillation on/off. 0: Turn off OSCX oscillator OXM: switching system clock. 0: select OSC as system clock
1: Turn on OSCX oscillator 1: select OSCX as system clock
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5.6. Programming Notes It takes at least 5 ms for the OSCX oscillation circuit to turn on until the oscillation stabilizes. When switching the CPU system clock from OSC to OSCX, the user must wait a minimum of 5ms since the OSCX oscillation is running. However, the start time varies with respect to oscillator characteristics and the condition of use. Thus the wait time depends on the application. When switching from OSCX to OSC, OSCX is turned off with one instruction. The OSCX turn off control will be delayed for one instruction cycle automatically to prevent CPU operation error. 6. I/O PORT The MCU provides 16 bi-directional I/O pads. The PORT data is put in register $08 - $0B. The PORT control register ($15 - $17, $19) controls the PORT as input or output. Each I/O port for PA3 - 1,PB, PC, PD has an internal pull-high resistor, which is controlled by PULLEN of $0C and the data of the port, when the PORT is used as input. Port I/O mapping address is shown as follows: Address $08 $09 $0A $0B $15 $16 $17 Bit3 PA.3 PB.3 PC.3 PD.3 PACR.3 PBCR.3 PCCR.3 TM04 Bit2 PA.2 PB.2 PC.2 PD.2 PACR.2 PBCR.2 PCCR.2 PDCR Bit1 PA.1 PB.1 PC.1 PD.1 PACR.1 PBCR.1 PCCR.1 Bit0 PA.0 PB.0 PC.0 PD.0 PACR.0 PBCR.0 PCCR.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W PORTA data PORTB data PORTC data PORTD data PORTA input/output control PORTB input/output control PORTC input/output control PORTD input/output control Remarks
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$19
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Each bit of the PORTA, PORTB and PORTC has its own direction-control bit, and the PORTD has one control bit only for all bits. .com PA (/B/C) CR.n, (n = 0, 1, 2, 3) 0: Set I/O as an input direction. (Power on initial) 1: Set I/O as an output direction. PDCR 0: Set PD3 - 0 as an input direction. (Power on initial) 1: Set PD3 - 0 as an output direction.
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SH67K91
Equivalent Circuit for PB3 - 0,PA3 - 1
VDD PULLEN VDD I/O Control Register Weak Pull high
DATA Regiser
I/O Pad
GND DATA READ DATA IN READ
Equivalent Circuit for PA0
VDD PA0_PEN PH/PL I/O Control Register Weak Pull high
VDD
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DATA Regiser
I/O Pad
GND
Weak Pull Low GND
DATA
READ DATA IN READ
Equivalent Circuit for PC3 - 0,PD3 - 0
VDD PULLEN VDD I/O Control Register Weak Pull high
O/S1 & O/S0
DATA Regiser
I/O Pad
GND DATA READ DATA IN READ LCD Segment
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SH67K91
6.1 System Register (PMOD) Address $0C Bit3 PPULL Bit2 HLM Bit1 OXM Bit0 OXON R/W R/W Remarks Bit2: Heavy load mode Bit3: Port pull-high control Bit3: Pull high/low resistor control bit of PA0 0: Pull high/low resistor disable 1: Pull high/low resistor enable Bit2: Pull-low resistor or pull-high resistor selection control bit of PA0 0: Pull-high resistor enable, Pull-low resistor disable 1: Pull-high resistor disable, Pull-low resistor enable
$2E
PA0_PEN
PL/PH
INT0_PA0 DACOUT_S R/W
HLM:
PPULL:
PA0_PEN:
PL/PH:
Enable heavy load mode 0: Disable 1: Enable Pull-high resistor control bit of PA3 - 1,PB, PC, PD 0: Disable pull-high resistor 1: Enable pull-high resistor Pull high/low resistor control bit of PA0 0: Pull high/low resistor disable 1: Pull high/low resistor enable Pull-low resistor or pull- high resistor selection control bit of PA0 0: Pull- high resistor enable, Pull-low resistor disable 1: Pull- high resistor disable, Pull-low resistor enable
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6.2 Heavy Load Mode (HLM) The MCU has a heavy load protection circuit for when the battery load becomes heavy, such as, when an external buzzer sounds or an external speaker is turned on. In this mode, the crystal oscillator circuit is backed-up for high gain. When this .com mode is set up, more power would be provided to an oscillator circuit. Unless it is necessary, avoid setting this mode with the software since the mode enterance would delay for one instruction. Please activate heavy load driving only after setting HLM for at least one instruction wait cycle through the software. The following shows the programming setting. HLM: 0 = Heavy load protection mode is released 1 = Heavy load protection mode is set.
HLM
0 1
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ON
HEAVYLOAD
OFF
1 Instruction Cycle Time
6.3. Port Interrupt The PORTB and PORTC are used as port interrupt sources. The following is the port interrupt function block-diagram.
IEP PORTB.n PORTC.n PBCR.n PCCR.n IRQP Note: n = 0, 1, 2, 3
Port Interrupt
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Port Interrupt (PBC INT) PROGRAMMING NOTES If user wants to generate an interrupt when a falling edge from VDD to GND emerges on the port, the following must be executed. 1. Set the port as input port, fill port data register with 1 and avoid port floating. 2. Pull-high the port (Use external pull high resistance or set PULLEN to 1). And further falling edge transition would not be able to make interrupt request until all of the pins are returned to VDD in PBC INT application. When PORTC is shared to segment, user can only generate interrupt on PORTB. 6.4. External Interrupt ( INT0 ) PA0 and FSKIN are shared by external interrupts (active low). 7. Timer0 SH67K91 has one 8-bit timer. The timer/counter has the following features: - 8-bit up-counting timer/counter. - Automatic re-load counter. - 8-level prescaler. - Interrupt on overflow from $FF to $00. The following is a simplified timer block diagram.
tosc System clock SYNC 8-BIT COUNTER
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Pre-Scaler
TM.2 TM.1 TM.0
The low-order digit should be written first, followed by the high-order digit. The timer/counter is automatically loaded with the contents of the load register when the high-order digit is written, or counter counts overflow from $FF to $00. Timer Load Register: The register H controls the physical READ and WRITE operations. Please follow these steps: Write Operation: Low nibble first High nibble to update the counter Read Operation: High nibble first Low nibble followed.
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The timers provide the following functions: - Programmable interval timer function. - Read counter value. 7.1. TIMER0 Configurations and Operation The Timer0 consists of an 8-bit write-only timer load register (TL0L, TL0H) and an 8-bit read-only timer counter (TC0L, TC0H). Each of them has both low-order digits and high-order digits. Writing data into the timer load register (TL0L, TL0H) can initialize the timer counter.
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Load Reg. L Load Reg. H
8-bit timer counter Latch Reg. L
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7.2. Timer0 Mode Register The timer can be programmed in several different prescalers by setting Timer Mode register (TM0). The 8-bit counter prescaler overflows output pulses. The Timer Mode register (TM0) is 3-bit register used for the timer control as shown in Table 1. The mode register selects the input pulse sources into the timer. The clock source of timer0 is selected by the TM0.4 control bit. Table 1. Timer0 Mode register TM0.3 0 0 0 0 0 0 0 0 1 1 TM0.2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TM0.1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TM0.0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Prescaler /2048 /512 /128 /32 /8 /4 /2 /1 /2048 /512 /128 Clock Source TM0.4=1($19.3) OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 OSC/4 TM0.4=0($19.3) System clock System clock System clock System clock System clock System clock System clock System clock System clock System clock System clock System clock System clock System clock System clock System clock Auto Reload No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes
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1 1 1 1 1 1
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/8 /4 /2 /1
/32
TM0.3 control function: 0: without Auto-Reload function for timer0 TM0.4 control function: 0: clock source of timer0 is system clock
1: Auto-Reload function for timer0 1: clock source of timer0 is OSC/4 clock
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8. Base Timer The MCU has a base timer that is shared with the warm-up timer and the clock source is OSC (Low frequency oscillation: Crystal 32.768kHz or RC 262kHz). After MCU is reset, it counts at every clock-input signal. When it counts to $FF, right after next clock input, counter counts to $00 and generates an overflow. This causes the interrupt of base timer interrupt request flag to 1.Therefore, the base timer can function as an interval timer periodically, generating overflow output as every 256th clock signal output. The timer accepts 4096Hz or 32.768kHz clock, and base timer generates an accurate timing interrupt. This clock-input source is selected by BTM register. Address $03 Bit3 BTM.3 1 Bit2 BTM.2 0 Bit1 BTM.1 X X BTC.5 BTC.1 Bit0 BTM.0 X X BTC.4 BTC.0 R R/W R/W Remarks Base timer mode register Enable the base timer Disable the base timer, clear base timer counters and keep them as $00 The counter register of base timer
Other states $06 $07 BTC.7 BTC.3 BTC.6 BTC.2 BTM.0 0 1 0 1
BTM.1 0 0 1 1
Prescaler Ratio /1 /4 /8 /16
Clock Source 4.096kHz or 32.768kHz 4.096kHz or 32.768kHz 4.096kHz or 32.768kHz 4.096kHz or 32.768kHz
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MPX
8 Bit base timer counter BTC7 - 0
32.768kHz or 262kHz
/8
4.096kHz/ 32.768kHz
4Bit Scaler
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BTM [3:2]
/1
/4
/8
/16
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SH67K91
9. LCD Driver The LCD driver contains a controller, a voltage generator, 8/4 common driver pads and 32 segment driver pads. There are 8 different driving programmable modes: 1/8 duty and 1/3 bias, 1/8 duty and 1/4 bias, 1/6 duty and 1/3 bias, 1/6 duty and 1/4 bias, 1/5 duty and 1/3 bias, 1/5 duty and 1/4 bias, 1/4 duty and 1/3 bias, 1/4 duty and 1/4 bias. The driving mode is controlled by the system register $14 and the power on initialization status is 1/8 duty, and 1/4 bias. The controller consists of display data RAM and a duty generator. The LCD SEG13 - 24 can also be used as output port, which is selected by the bit 2 of the system register $13. When SEG13 - 24 are selected to be output port, one should write data to RAM addresses ($28 - $2A). The LCD SEG25 - 32 can also be used as I/O port (PORTC and PORTD), which is selected by bit 1,0 of the system register $13. LCD RAM could be used as data memory if needed. When the "STOP" instruction is executed, the LCD will be turned off, but the data of LCD RAM would still retain the value. When LCD is off, both common and segment outputs are low. 9.1. LCD Control Register Address $0D $13 Bit 3 RAMBNK LCDON Bit 2 LCM2 O/S2 Bit 1 LCM1 O/S1 Bit 0 LCM0 O/S0 R/W Remarks
R/W Bit2 - 0: LCD contrast adjustment register Bit1 - 0: segment/PORTC - D sharing control bits R/W Bit2: Segment/scan output control bit for segment13 - 24 Bit3: LCD on/off control bit
$14 $28 $29 $2A
COM_M1 COM_MD0 SEG24 SEG20 SEG16 SEG23 SEG19 SEG15
BIAS SEG22 SEG18 SEG14
Bit0: Lcd frame frequency selection bit LCD_FREQ R/W Bit1: Lcd Bias selection bit Bit3 - 2: duty selection bit SEG21 R/W Data Register of LCD SEG24 - 21 when SEG24 - 21 shared as output port.
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Data Register of LCD SEG20 - 17 when SEG20 - 17 SEG17 R/W shared .com as output port. SEG13 R/W Data Register of LCD SEG16 - 13 when SEG16 - 13 shared as output port.
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LCD ON/OFF control and LCD shared control register Address $13 Bit 3 LCDON 0 1 X X X X X Bit 2 O/S2 X X 0 1 X X X Bit 1 O/S1 X X X X 0 0 1 Bit 0 O/S0 X X X X 0 1 X R/W Remarks
R/W LCD ON/OFF control and LCD shared control LCD OFF LCD ON Segment13 - 24 set as segment signal of LCD Segment13 - 24 set as output port Segment25 - 32 shared as LCD Segment output Segment29 - 32 shared as PORTC3-PORTC0 Segment28 - 25 shared as LCD Segment output Segment29 - 32 shared as PORTC3-PORTC0 Segment28 - 25 shared as PORTD3-PORTD0
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LCD Duty and Bias setting register Address $13 Bit 3 Bit 2 Bit 1 BIAS X X X X 0 1 X X Bit 0 R/W Remarks
COM_MD1 COM_MD0 0 0 1 1 X X X X 0 1 0 1 X X X X
LCD_FREQ R/W X X X X X X 0 1 LCD driver = 1/8 duty LCD driver = 1/6 duty, COM8 - 7 output unselected level LCD driver = 1/5 duty, COM8 - 6 output unselected level LCD driver = 1/4 duty, COM8 - 5 output unselected level LCD driver = 1/4 bias LCD driver = 1/3 bias LCD frame frequency = 64Hz LCD frame frequency = 32Hz
COM1
COM1
ONE
FRAME
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When the CPU is in the STOP mode, the COMx and SEGx are pulled low. It can easily be woken up by a keyboard scan (Port .com interrupt). When the CPU is in the HALT mode, the COMx and SEGx are normal. It can easily be woken up by base timer timer0 or port interrupt.
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9.2. Configuration of LCD RAM Segment1 - 32, 1/8 duty Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Address $320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32A $32B $32C $32D $32E $32F $331 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F Bit3 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit2 COM7 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
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.com SEG17 SEG17 $330
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SH67K91
Segment1 - 32, 1/6 duty Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Address $320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32A $32B $32C $32D $32E $32F $330 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
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.com SEG18 $331
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Segment1 - 32, 1/5 duty Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Address $320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32A $32B $32C $32D $32E $32F $330 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
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.com SEG18 $331
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Segment1 - 32, 1/4 duty Address $300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
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DataShee
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SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
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9.3 LCD Power
VDD OSC/64 Power regualtor LCD OFF LCDM2 - 0 /2 COM_MD1 - 0 LCD_FREQ
BIAS
LCD Power Supply Control Circuit
LCD common driver
COM1 - COM8
LCD SEG1 - SEG32 segment driver
The contrast control register can adjust the contrast of LCD. Address $0D Bit 3 RAMBNK Bit 2 LCM2 Bit 1 LCM1 Bit 0 LCM0 R/W R/W Remarks Bit2 - 0: LCD contrast adjustment register
LCDM2
LCDM1 0 0 1 1 0 0 1 1
LCDM0 0 1 0 1 0 1 0 1
VLCD/VDD Mainchip EV 0.60 0.70 0.90 0.95 1.00 1.00 1.00
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0 0 0 0 1 1 1 1
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0.70 0.82 0.88 0.94 1.00 1.00 1.00
.com0.65 0.76
Note: There is some difference for LCD contrast level setting between mainchip and EV chip. For mainchip, the VLCD level setting is linear from 0.7VDD to VDD and the step is 0.06VDD, and for EV chip, the VLCD level setting is non-linear from 0.6VDD to VDD.
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9.4 LCD Waveform
1/8 DUTY 1/4 BIAS SELECT UNSELECT VLCD V1 V2 COM V3 GND SELECT UNSELECT VLCD V1 SEG V2 V3 GND SEG SELECT UNSELECT VLCD V1 V2 GND COM 1/4 DUTY 1/3 BIAS SELECT UNSELECT VLCD V1 V2 GND
Example: 1/8 duty, 1/4 bias
VLCD V1 COM1 V2 V3
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GND
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VLCD V1 COM2 V2 V3 GND
VLCD V1 COM3 V2 V3 GND
VLCD V1 SEG V2 V3 GND
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10. Interrupt Four interrupt sources are available on SH67K91: - External interrupt ( INT0 ) - Timer0 interrupt - Base Timer interrupt - Port's falling edge detection interrupt ( INT1 ) Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program. Those flags are cleared to "0" at initialization by the chip reset. System Register Address $00 $01 Bit 3 IEX IRQEX Bit 2 IET0 IRQT0 Bit 1 IEBT IRQBT Bit 0 IEP IRQP R/W R/W R/W Reamrks 1: Enable/0: Disable 1: Request/0: No request IRQ_PA0: 1: PA0 interrupt Request 0: No request IRQ_FSKIN: 1: FSKIN interrupt Request 0: No request
$18
IRQ_PA0
IRQ_FSKIN
B1
B0
R/W
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When IEx is set to "1" and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx) are reset to "0" automatically, so when IRQx is 1 and IEx is set to "1" again, the interrupt will be activated and vector address will .com be generated from the priority PLA corresponding to the interrupt sources.
Inst.cycle 1 2 3 4 5
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Instruction Execution N
Instruction Execution I1
Instruction Execution I2
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start at vector address
Interrupt Servicing Sequence Diagram Interrupt Nesting During the CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the instruction of execution N is IE enabled, then the interrupt will start immediately after the next two instruction executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be terminated.
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External Interrupt ( INT0 ) Interrupt 0 is shared with the PORTA0, the FSK receiver, falling edge active. When the bit 3 of the register $0 (IEX) is set to 1, the interrupt0 is enabled. Writing a "0" to PA0 will generate an external interrupt. When the an interrupt0 occurred, one must read the IRQPA0, IRQ_FSKIN first to judge the interrupt source is from PA0, the FSK receiver. IEX: Interrupt0 on/off switch. 0: disable. 1: Enable IRQEX: Interrupt0 interrupt request 0: No request 1: Request IRQ_PA0: PA0 interrupt request 0: No request 1: Request IRQ_FSKIN: FSK receiver interrupt request 0: No request 1: Request
FSKIN_STAT
IRQ_FSKIN
IRQ_PA0
FSK receiver
IEX0
CPU
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PA0
IRQEX0
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Note: While external interrupt is enabled, writing a "1" (or "0") to the external interrupt I/O port will generate an external interrupt. Timer Interrupt The input clocks of Timer0 and Base Timer are based on system clock. The timers overflow from $FF to $00 will generate an internal interrupt request (IRQT0 or IRQBT1 = 1), If the interrupt enable flag is enabled (IET0 or IEBT1 = 1), a timer interrupt service routine will start. Timer interrupt can also be used to wake the CPU from the HALT mode. Port Falling Edge Interrupt Only the digital input port can generate a port interrupt. The analog input cannot generate an interrupt request. Any one of the I/O input pin transitions from VDD to GND would generate an interrupt request (IRQP = 1). Further falling edge transition would not be able to make a new interrupt request until all of the input pins have returned to VDD. Port Interrupt can be used to wake the CPU from the HALT or the STOP mode.
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PORTX.3 PXCR.3 Port interrupt request generator IEP PORTX.1 PXCR.1 Falling edge Detector X = B, C Falling edge Detector
PORTX.2 PXCR.2
Falling edge Detector
Interrupt CPU
PORTX.0 PXCR.0
Falling edge Detector
Port Interrupt Block Diagram
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11. 4/8 Channels Chords/ 9bit DAC Melody Prescaler /DTMF Generator/DAC data register Address $1A $1B $1C Bit3 DAC_S3 CH_M TONE7 DG7 DA7 TONE3 DG3 DA3 VOL 3 PA0_PEN Bit2 DAC_S2 CH_S2 TONE10 DG10 TONE6 DG6 DA6 TONE2 DG2 DA2 VOL 6 VOL 2 PL/PH Bit1 DAC_S1 CH_S1 TONE 9 DG9 TONE5 DG5 DA5 TONE1 DG1 DA1 VOL 5 VOL 1 INT0_PA0 Bit0 DAC_S0 CH_S0 TONE 8 DG8 DA8 TONE4 DG4 DA4 TONE0 DG0 DA0 VOL 4 VOL 0 DACOUT_S R/W R/W Volume register DAC output pad selection R/W Tone prescaler DTMF Generator Presacler DAC data register R/W R/W R/W Remarks DAC function control register Chord mode control bit, and Channel control register
$1D
$1E $20 $21 $2E CH_M:
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CH_S2 - 0: TONE10 - 8/DG10 - 8/DA8: TONE7 - 4/DG7 - 4/DA7 - 4: TONE3 - 0/DG3 - 0/DA3 - 0
VOL6 - 0: DAC_S3 - 0: DACOUT_S:
the chord type select bit 0: 4 or less 4 channels chords 1: 8 or more 4 channel schords the index bits of eight channel for setting the prescaler and volume register. the High nibble of Prescaler register of Tone generator or high nibble of DAC data .com the Middle nibble of Prescaler register of Tone generator or middle nibble of DAC data the Low nibble of Prescaler register of Tone generator or low nibble of DAC data While writing DAC data or prescaler data, please writing the Low nibble first, then middle nibble and the high nibble at last. the volume register Tone generator While writing Volume data, please write the Low nibble first, then the high nibble. the operation mode setting of DAC the DAC output pad selection control bit 0: DAC output from TONE Pad 1: DAC output from DACOUT Pad
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DAC_S3 DAC_S2 DAC_S1 DAC_S0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 x 0 0 1 1 0 0 1 1 0 1 0 1 x 0 1 0 1 0 1 0 1 Channel 1 enable Channel 1 - 2 enable Channel 1 - 3 enable Channel 1 - 4 enable Channel 1 - 5 enable Channel 1 - 6 enable Channel 1 - 7 enable Channel 1 - 8 enable Melody DTMF Generaotr (DAC data is from the Melody) All Disable All Disable All Disable Disable Disable Enable Reserved Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable DAC (DAC data is from the DA8 - 0) Disable Enable Disable
When DAC_S3 - 0 = 0000, the power of meoldy modulator block and DAC block is off.
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OSCX/32 1: Tone10 - 0 Tone10 - 0 1: Vol6 - 0
Channel1 Prescaler
Modulator
VOL6 - 0
2: Tone10 - 0 2: Vol6 - 0
Channel2 Prescaler
Modulator
DAC_S3 - 0 channel 3 - 6 CH_S3 - S0
TONE
Mixer Output
DAC
DACOUT
7: Tone10 - 0 7: Vol6 - 0
Channel7 Prescaler
Modulator
8: Tone10 - 0 8: Vol6 - 0
Channel8 Prescaler
Modulator
DACOUT_S
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Melody Block Diagram
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OSCX/2 1: Tone10 - 0 DG10 - 0
Channel1 Row Freq Prescaler
Modulator
CH_S3 - S0
2: Tone10 - 0
Channel2 Column Freq Prescaler
Modulator
TONE
DA8 - 0
TONE
Mixer Output
DAC
DACOUT
DAC
DACOUT
DAC_S3 - 0
DACOUT_S
DACOUT_S
Speech Block Diagram(using DAC directly)
DTMF Generator Block Diagram
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12. STOP/HALT Mode After the execution of the HALT instruction, SH67K91 will enter the HALT mode. In the HALT mode, CPU will STOP operating. But peripheral circuit (Timer, Base timer, ...etc.) will keep the same status. After the execution of the STOP instruction, SH67K91 will enter the STOP mode. The whole chip (including oscillator) will STOP operating. In the HALT mode, SH67K91 can be waked up if any interrupt occurs. In the STOP mode, SH67K91 can be waked up if port interrupt occurs. When CPU is awaked from the HALT/STOP by any initial source, it will execute the relevant initial serve subroutine at first. Then the next instruction is executed. STOP/HALT mode STOP HALT 13. Warm-up Timer The device has a built-in warm-up timer to eliminate unstable state of initial oscillation when oscillator starts oscillating in the following conditions: 13.1. Power-on Reset Warm-up time interval: (1) In RC oscillator mode, the warm-up counter prescaler divide ratio is /27 (128). (2) In Crystal oscillator or Ceramic resonator mode, the warm-up counter prescaler divide ratio is /212 (4096). 13.2. Wake-up from the STOP Mode .com Warm-up time interval: (1) In RC oscillator mode, the warm-up counter prescaler divide ratio is /212 (4096). 12 (2) In Crystal oscillator or Ceramic resonator mode, the warm-up counter prescaler divide ratio is /2 (4096). The clock source of warm-up timer is system clock. System clock is unchange When system return from STOP mode. Oscillator OSC Stop OSCX Stop OSC live OSCX live CPU core Hold Hold Wake up RST , INT0 , INT1 RST , INT0 , INT1 , T0INT, BTINT
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14. Bonding Option System Register: Address Bit 3 Bit 2 Bit 1 B1 0 $18 0 1 1 Bit 0 B0 1 0 1 0 R/W R R R R R Remarks B1, B0: Bonding option Default bonding option B0 bond to GND B1 bond to AVDD B0 bond to GND & B1 bond to AVDD
IRQ_PA0 IRQ_FSKIN
B0 GND
AVDD B1
B0 GND
AVDD B1
PCB
B0 = 1 B0
B1 = 0 AVDD B1
B0 = 1 B0 GND
B1 = 1 AVDD B1
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GND
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PCB B0= 0 B1 = 0
B0 = 0
B1 = 1
Up to 4 different bonding options are possible for user's needs. The chip's program has 4 different program flows that varies depending on which bonding option is used. The readable contents of B1 and B0 will differ depending on bonding. 15. Code Option C: OSC clock source 0: 32.768kHz crystal 1: 262kHz RC L: OSCX clock source 0: 455kHz - 4MHz ceramic 1: 4MHz RC
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16. Instruction Set All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation. 16.1. Arithmetic and Logical Instruction 16.1.1. Accumulator Type Mnemonic ADC X (, B) ADCM X (, B) ADD X (, B) ADDM X (, B) SBC X (, B) SBCM X (, B) SUB X (, B) SUBM X (, B) EOR X (, B) EORM X (, B) OR X (, B) ORM X (, B) Instruction Code 00000 0bbb xxx xxxx 00000 1bbb xxx xxxx 00001 0bbb xxx xxxx 00001 1bbb xxx xxxx 00010 0bbb xxx xxxx 00010 1bbb xxx xxxx 00011 0bbb xxx xxxx 00011 1bbb xxx xxxx 00100 0bbb xxx xxxx 00100 1bbb xxx xxxx 00101 0bbb xxx xxxx 00101 1bbb xxx xxxx 00110 0bbb xxx xxxx 00110 1bbb xxx xxxx 11110 0000 000 0000 Function AC <- Mx + AC + CY AC, Mx <- Mx + AC + CY AC <- Mx + AC AC, Mx <- Mx + AC AC <- Mx + -AC + CY AC, Mx <- Mx + -AC + CY AC <- Mx + -AC +1 AC, Mx <- Mx + -AC +1 AC <- Mx AC AC, Mx <- Mx AC AC <- Mx | AC AC, Mx <- Mx | AC AC <- Mx & AC Flag Change CY CY CY CY CY CY CY CY
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AND X (, B) ANDM X (, B) SHR 16.1.2. Immediate Type Mnemonic ADI X, I ADIM X, I SBI X, I SBIM X, I EORIM X, I ORIM X, I ANDIM X, I
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AC, Mx <- Mx & AC CY
0 -> AC [3], AC [0] -> CY; AC shift right one bit
Instruction Code 01000 iiii xxx xxxx 01001 iiii xxx xxxx 01010 iiii xxx xxxx 01011 iiii xxx xxxx 01100 iiii xxx xxxx 01101 iiii xxx xxxx 01110 iiii xxx xxxx
Function AC <- Mx + I AC, Mx <- Mx + I AC <- Mx + -I +1 AC, Mx <- Mx + -I +1 AC, Mx <- Mx I AC, Mx <- Mx | I AC, Mx <- Mx & I
Flag Change CY CY CY CY
16.1.3. Decimal Adjustment Mnemonic DAA X DAS X Instruction Code 11001 0110 xxx xxxx 11001 1010 xxx xxxx Function AC, Mx <- Decimal adjust for add AC, Mx <- Decimal adjust for sub Flag Change CY CY
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16.2. Transfer Instruction Mnemonic LDA X (, B) STA X (, B) LDI X, I 16.3. Control Instruction Mnemonic BAZ X BNZ X BC X BNC X BA0 X BA1 X BA2 X BA3 X CALL X Instruction Code 10010 xxxx xxx xxxx 10000 xxxx xxx xxxx 10011 xxxx xxx xxxx 10001 xxxx xxx xxxx 10100 xxxx xxx xxxx 10101 xxxx xxx xxxx 10110 xxxx xxx xxxx 10111 xxxx xxx xxxx 11000 xxxx xxx xxxx 11010 000h hhh llll 11010 1000 000 0000 11011 0000 000 0000 11011 1000 000 0000 1110p xxxx xxx xxxx 11110 1111 111 1111 11111 1111 111 1111 PC <- X (Include p) PC <- (PC11-PC8) (TBR) (AC) No Operation Function PC <- X, if AC = 0 PC <- X, if AC 0 PC <- X, if CY = 1 PC <- X, if CY 1 PC <- X, if AC (0) = 1 PC <- X, if AC (1) = 1 PC <- X, if AC (2) = 1 PC <- X, if AC (3) = 1 ST <- CY, PC +1 PC <- X (Not include p) PC <- ST; TBR <- hhhh, AC <- lll CY, .com PC <- ST CY Flag Change Instruction Code 00111 0bbb xxx xxxx 00111 1bbb xxx xxxx 01111 iiii xxx xxxx Function AC <- Mx Mx <- AC AC, Mx <- I Flag Change
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RTNW H, L RTNI HALT STOP JMP X TJMP NOP Where, PC AC -AC CY Mx p ST
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Program counter Accumulator Complement of accumulator Carry flag Data memory ROM page Stack
I | & bbb
Immediate data Logical exclusive OR Logical OR Logical AND RAM bank
TBR
Table Branch Register
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17. Chord Table Following is the chord scale reference table for all channel under OSCX = 4MHz. (Up to 6 octaves are possible) Note B1 C2 #C2 D2 #D2 E2 F2 #F2 G2 #G2 A2 #A2 B2 C3 #C3 D3 #D3 E3 F3 #F3 G3 #G3 A3 #A3 B3 C4 #C4 D4 #D4 E4 F4 #F4 G4 #G4 A4 #A4 B4 Ideal freq. 61.73 65.10 69.29 73.42 77.78 82.41 87.31 92.50 98.00 103.82 110.00 116.54 123.47 130.81 138.59 146.83 155.56 164.81 174.61 184.99 196.00 207.65 220.00 233.08 246.94 261.63 277.18 293.66 311.12 329.63 349.23 369.99 392.00 415.30 440.00 466.15 493.88 N 2024 1919 1803 1702 1606 1516 1431 1350 1275 1203 1135 1072 1011 955 901 850 803 757 715 675 637 601 567 535 505 477 450 425 401 378 357 337 318 300 283 267 252 Tone Real freq. Error% Note Prescaler 7E8 77F 70B 6A6 646 5EC 597 546 4FB 4B3 46F 430 3F3 3BB 385 352 323 2F5 2CB 2A3 27D 259 237 217 1F9 1DD 1C2 1A9 191 17A 165 151 13E 12C 11B 10B FC 61.73 65.10 69.29 73.40 77.78 82.40 87.29 92.52 97.96 103.82 110.04 116.50 123.52 130.75 138.58 146.89 164.91 174.58 184.91 195.92 207.64 220.07 233.21 247.04 261.51 277.16 293.43 310.95 329.82 349.16 369.82 391.85 415.28 440.14 466.42 494.07 0.00 -0.01 0.00 0.03 -0.01 0.01 0.02 -0.03 0.04 0.00 -0.03 0.04 -0.04 0.04 0.01 -0.04 -0.06 0.02 0.04 0.04 0.00 -0.03 -0.06 -0.04 0.05 0.01 0.08 0.06 -0.06 0.02 0.05 0.04 0.00 -0.03 -0.06 -0.04 B4 C5 #C5 D5 #D5 E5 F5 #F5 G5 #G5 A5 #A5 B5 C6 #C6 D6 E6 F6 #F6 G6 #G6 A6 #A6 B6 C7 #C7 D7 #D7 E7 F7 #F7 G7 #G7 A7 #A7 B7 Ideal freq. 493.88 523.25 554.35 587.33 622.24 659.26 698.46 739.97 783.99 830.59 880.00 932.31 987.77 1046.48 1108.71 1174.63 1318.48 1396.88 1479.95 1567.95 1661.18 1759.96 1864.62 1975.49 2092.96 2217.41 2349.27 2488.96 2636.96 2793.77 2959.89 3135.90 3322.37 3519.93 3729.23 3950.98 N 252 238 224 212 200 189 178 168 158 149 141 133 126 118 112 105 99 94 88 83 79 74 70 66 62 59 55 52 49 46 44 41 39 37 35 33 31 Tone Real freq. Error% Prescaler FC EE E0 D4 C8 BD B2 A8 9E 95 8D 85 7E 76 70 69 63 5E 58 53 4F 4A 46 42 3E 3B 37 34 31 2E 2C 29 27 25 23 21 1F 494.07 523.01 555.56 586.85 621.89 657.89 698.32 739.64 786.16 833.33 880.28 932.84 984.25 1050.42 1106.19 1179.25 1250.00 1315.79 1404.49 1488.10 1562.50 1666.67 1760.56 1865.67 1984.13 2083.33 2232.14 2358.49 2500.00 2659.57 2777.78 2976.19 3125.00 3289.47 3472.22 3676.47 3906.25 -0.04 0.05 -0.22 0.08 0.06 0.21 0.02 0.04 -0.28 -0.33 -0.03 -0.06 0.36 -0.38 0.23 -0.39 -0.44 0.20 -0.55 -0.55 0.35 -0.33 -0.03 -0.06 -0.44 0.46 -0.66 -0.39 -0.44 -0.86 0.57 -0.55 0.35 0.99 1.36 1.41 1.13
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DTMF Generator Tone Register: (under OSCX = 4MHz.) Channel 2 Prescaler Channel 1 Prescaler $059 $050 $048 $041 COL ROW 697Hz 770Hz 852Hz 941Hz $033 1209Hz 1 4 7 # $02E 1336Hz 2 5 8 0 $029 1477Hz 3 6 9 $025 1633Hz A B C D
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Electrical Characteristics
Absolute Maximum Rating* DC Supply Voltage . . . . . . . . . . . . . . . -0.3V to +7.0V Input Voltage . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Ambient Temperature . . . . -10 to +60 Storage Temperature . . . . . . . . . . . . -55 to +125 *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25, fOSC = 32.768kHz, fOSCX is not used, unless otherwise specified) Parameter Operating Voltage Operating Current Standby Current Standby Current Symbol VDD IOP ISB1 ISB2 VIH VIL VIH VIL ROH VOH1 VOL1 VOH2 VOL2 RLCD RON Min. 2.4 0.7 X VDD -0.3 0.85 X VDD -0.3 0.7 X VDD VDD - 0.6 Typ. 3.0 10 2 200 235 5 Max. 5.5 20 4 1 VDD + 0.3 0.3 X VDD Unit V A A A V V All output pads unload execute NOP instruction excluding LCD bias current and FSK recevier All output pads unload (HALT mode) excluding LCD bias current and FSK recevier All output pads unload (STOP mode), LCD off and excluding FSK recevier PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC, PORTD Conditions
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Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Pull -high Resistance Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage LCD Voltage Divider Resistor LCD Driving on resistor
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0.15 X VDD 0.8 0.8 V k V V V V k k LCD COM1 - 8, LCD SEG1 - 32, the voltage variation of V1, V2, V3, V4 is less than 0.2V. INT0 , RESET (Schmitt trigger input) PORTA - D (IOH = 10A) PORTA - D (IOH = 2mA) PORTA - D (IOL = -2mA) SEG13 - 24 to be output port, IOH = 1mA SEG13 - 24 to be output port, IOL = -1mA
HLM vs. IOP, ISB1 and ISB2 If HLM = 1, IOPX = IOP X 2, ISB2X = ISB2 X 2.
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DC Electrical Characteristics (Continued) (VDD = 5.0V, GND = 0V, TA = 25, fOSC = 32.768kHz, fOSCX is not used, unless otherwise specified) Parameter Operating Voltage Operating Current Standby Current Standby Current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Pull-high Resistance Output High Voltage Output Low Voltage Output High Voltage Symbol VDD IOP ISB1 ISB2 VIH VIL VIH VIL ROH VOH1 VOL1 VOH2 VOL2 RLCD RON Min. 2.4 0.7 X VDD -0.3 0.85 X VDD -0.3 0.7 X VDD VDD - 0.6 Typ. 5.0 20 5 200 Max. 5.5 40 10 1 VDD + 0.3 0.3 X VDD VDD + 0.3 0.15 X VDD 0.8 0.8 Unit V A A A V V V V k V V V V All output pads unload execute NOP instruction excluding LCD bias current and FSK recevier All output pads unload (HALT mode) excluding LCD bias current and FSK recevier All output pads unload (STOP mode), LCD off and excluding FSK recevier PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC, PORTD INT0 , RESET (Schmitt trigger input) INT0 , RESET (Schmitt trigger input) PORTA - D (IOH = 10A) PORTA - D (IOH = 3mA) PORTA - D (IOL = -3mA) SEG13 - 24 to be output port, IOH = 1mA SEG13 - 24 to be output port, IOL = -1mA Conditions
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Output Low Voltage LCD Voltage Divider Resistor LCD Driving on resistor
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k 235 .com 5 k LCD COM1 - 8, LCD SEG1 - 32, the voltage variation of V1, V2, V3, V4 is less than 0.2V.
HLM vs. IOP, ISB1 and ISB2 If HLM = 1, IOPX = IOP X 2, ISB2X = ISB2 X 2. AC Characteristics (VDD = 3.0V, GND = 0V, TA = 25, fOSC = 32.768kHz, unless otherwise specified) Parameter Oscillation Start Time Frequency Stability Symbol tSTT |f|/f Min. Typ. 1 Max. 2 1 Unit s PPM Conditions 32.768kHz Crystal Oscillator [f (3.0) - f (2.5)] /f (3.0), 32.768kHz Crystal Oscillator
AC Characteristics (VDD = 5.0V, GND = 0V, TA = 25, fOSC = 32.768kHz, unless otherwise specified) Parameter Oscillation Start Time Frequency Stability Symbol tSTT |f|/f Min. Typ. 1 Max. 2 1 Unit s PPM Conditions 32.768kHz Crystal Oscillator [f (5.0) - f (4.5)] /f (5.0), 32.768kHz Crystal Oscillator
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RC Oscillator Characteristics Graphs (for reference only)
RC Oscillator (OSC) Resistor vs Frequency (VDD = 3.0V)
700
600 OSC Frequency (kHz)
500
400
300
200
100
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70
90
110
130 Resistor (k)
150
170
190
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RC Oscillator (OSC) Resistor vs Frequency (VDD = 5.0V)
700 600 OSC Frequency (kHz) 500 400 300 200 100 50 70 90 110 130 Resistor (k) 150 170 190
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RC Oscillator Characteristics Graphs (Continued)
RC Oscillator (OSCX) Resistor vs Frequency (VDD = 3.0V)
10 9 OSCX Frequency (MHz) 8 7 6 5 4 3 2 50 70 90 110 130 Resistor (k) 150 170 190
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RC Oscillator (OSCX) Resistor vs Frequency .com (VDD = 5.0V)
10 9 OSCX Frequency (MHz) 8 7 6 5 4 3 2 50 70 90 110 130 Resistor (k) 150 170 190
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RC Oscillator Characteristics Graphs (Continued)
RC Oscillator (OSC) Frequency vs Voltage (VDD)
300 OSC Frequency (kHz) 250 200 150 100 50 0 2.2 2.7 3.2 3.7 VDD (V) 4.2 4.7 5.2
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RC Oscillator (OSCX) Freqency vs Voltage (VDD) .com
4.5 4 OSCX Freqency (MHz) 3.5 3 2.5 2 1.5 1 0.5 0 2.2 2.7 3.2 3.7 VDD (V) 4.2 4.7 5.2
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Bonding Diagram
SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6
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SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 PORTB0 PORTB1 PORTB2 PORTB3 PORTA0 PORTA1 PORTA2 PORTA3 B0 GND RING TIP AVDD B1 DACOUT TONE
20 19 18 17 16 15 14 13 12 11 10 9 8 7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG5
42 43 44
SEG4 SEG3 SEG2 SEG1 COM1 COM2 COM3 COM4
SH67K91
Y
45 46 47 48 49 50 51 52 53
COM6 COM7 COM8
X (0,0)
54
55 6 5 4 3 56 57 58 59 60 61
VDD OSCO OSCI OSCXO OSCXI RESET TEST
2 1
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Pad Location Pad No. 1 2 Bonding Option 3 4 5 6 Bonding Option 7 8 9 10 11 12 13 14 15 16 17 18 19 Designation TONE DACOUT B1 AVDD TIP RING GND B0 PORTA3 PORTA2 PORTA1 PORTA0 PORTB3 PORTB2 PORTB1 PORTB0 SEG32 SEG31 SEG30 SEG29 SEG28 X -1365 -1365 -1299 -1299 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365
3000um
2700um
COM5
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Y -1208 -1078 -946.5 -850 -711.5 -596.5 -486.5 -389.5 -282.5 -172.5 -62.5 47.5 157.5 267.5 377.5 487.5 597.5 707.5 827.5 947.5 1077.5 Pad No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Designation SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 X -1365 -1187 -1057 -927 -807 -697 -587 -477 -367 -257 -147 -37 73 183 293 403 513 623 733 843 963
unit:m
Y 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5 1207.5
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Pad Location (Continued) Pad No. 41 42 43 44 45 46 47 48 49 50 51 Designation SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM1 COM2 COM3 COM4 COM5 X 1093 1223 1365 1365 1365 1365 1365 1365 1365 1365 1365 Y 1207.5 1207.5 1116 986 856 736 616 506 396 286 176 Pad No. 52 53 54 55 56 57 58 59 60 61 Designation COM6 COM7 COM8 VDD OSCO OSCI OSCXO OSCXI RESET TEST X 1365 1365 1365 1365 1365 1365 1365 1365 1365 1365 Y 66 -44 -154 -374 -484 -594 -714 -834 -964 -1094
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Ordering Information
Part No. SH67K91-yyxxx/061HR Package CHIP Packing TRAY
Note: (1) "-yyxxx": "yy" means 2 bits option and "xxx" means 3 bits code seriary number. If the product is OTP type and in blank order, those bits should be none. (2) The data after mark "/" in Part No. block is the package and packing information for ordering. (3) Any other package or packing request, please refer to following table. Package D F H J K L M N DIP QFP CHIP CER-DIP SKINNY PLCC SOP OTHER GOOD DIE ON WAFER SOJ TO92 VSOP/TSOP WAFER TSSOP R U A D L B T S N Packing Normal package size and in tray packing Normal package size and in tube packing Normal package size and in tape & reel packing Larger package size and in tray packing Larger package size and in tube packing Larger package size and in tape & reel packing Smaller package size and in tray packing Smaller package size and in tube packing Smaller package size and in tape & reel packing
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Data Sheet Revision History
The following table shows the revision history for this document Revision No. 1.0 Original History Date Nov. 2004
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